High speed print synchronizer



Feb. 21, 1967 WEI MING SHIH HIGH SPEED PRINT SYNCHRONIZER 19 Sheets-Sheet 1 Filed July 10, 1963 a R e REG 000 I.

REG EVEN I.

N D E W T TV 9 G G R R R m L M s 4 R YS a m m l $3 GET CI MRN G x R w F 8 E Y. R 0 M E M A CHARACTOR 3 ODD MSC 0R CHAR ACTOR I ODD BIT POSITION Efimw-- ODD REG 5s N E V TL n/L R 0 III C AI R A H C0 0 NT E VII E 4 RI 0 I C A R A H C R 0 CO S I 8 5 G E R N E V E lNSTRUCTION FOR PRINTING 8x PAPER ADVANCE IRE? I I FGSIIION fI-EII REG 5B GUI] REG 56 L-ADDRESS FUNCTION CODE LINES OF VERTICAL SPACING BITS VIM Dn 40 WW DE R Lt rC AVCLH TI N NEH W I. N H S I mM B mmm L.L WW U a C R V Gm B I F 3 F flu O III F 2 F 0 IIIIOU F I 0 OO O E R U T 0 25456 A T s R Feb. 21, 1967 WEI MING SHIH 3,305,840

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HIGH SPEED PRINT SYNCHRONIZER Filed July 10, 1963 19 Sheets-Sheet 1;

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Filed July 10, 1965 FIG. 14o

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Feb. 21, 1967 Filed July 10, 1963 U 10 9' LL IO 9' LI- M 99 9Q 11.11. 3 5 Q 2' mu.

WEI MING SHIH 3,305,840

HIGH SPEED PRINT SYNCHRONIZER l9 Sheets5heet 1 Feb. 21, 1967 WEI MING SHIH 3,305,840

HIGH SPEED PRINT SYNCHRONIZER Filed July 10, 1963 19 sheets sheet 1.;

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Feb. 21, 1967 HIGH STE-E1) Filed July 10, 1965 iFlG. FIG. 516a 16bi INERMEEWG W l RESH CODE WHEEL CTR P, )HFSET BINARY CTR P18 NIL" w :1 men awn FH mm RESET smc FFI.

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TRENT SYNCHRONIZLR l9 Sheets-Sheet 1 FIG. 16a

Feb. 21, 1967 WEI MING SHIH HIGH SPEED PRINT SYNCHRONIZER l9 Sheets-Sheet 1 Filed July 10, 1963 FIG. 16b

D m R F. P T E K C 0 R P S T X E N United States Patent Ofilicc 3,305,840 Patented Feb. 21, 1967 3,305,840 HIGH SPEED Pl'llNT SYNCHRONIZER Wei Ming Shih, deceased, late of Flourtown, Pa., by Phoebe H. Y. Shit], exccutrix, Flour-town, Pa., and Robert L. Bast, executor, Ambler, Pa., assignors to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed July 10, 1963, Ser. No. 2%,206 30 Claims. (Cl. 34l]172.5)

This invention relates to a high speed print synchronizer and more particularly to a device which is capable of accepting information at a random time sequence, print infomation as it is available and keep track of information which has been received as well as that which has been printed out.

Data processing systems which are currently in use, consist mainly of a central processing unit and a plurality of devices known as peripheral equipment. Peripheral equipment may consist, for example, of typewriter or keyboard-type units, high and low speed tape units, punch card reader and sensing devices, card punching devices, printing devices and cathode ray displays. These peripheral units may be connected to supply information to the central processor or receive information therefrom.

In order to prevent the peripheral device from attempt ing to feed or receive information from the central proces sor at the same time, a system known as priority is estab lished. A priority number is assigned to each type of equipment and to individual pieces of equipment within the type. Thus, a particular tape unit will have a priority assigned to it which reflects the priority of the tape units with regard to the other peripheral equipment and of the particular tape unit with regard to the other tape units. Priority assignments may be made on the basis of relative speed of operation of the peripheral unit with respect to the central processor, that is rate of transfer of data.

The priority assignments are used in conjunction with circuitry to control the transfer of information between the peripheral equipment and the memory of the central processor. Thus, for example when the memory is available to accept information a check will be made of all peripheral equipment desiring access to the memory and the request of the equipment with the highest priority will be granted. If during such a memory access, a unit of higher priority requests access to the memory, then the access of the first equipment will be interrupted at some convenient termination point. Then the unit of higher priority will take over until it has completed its use of the memory. At this time, the first unit may again obtain the use of the memory providing another unit of higher priority has not made a memory request.

ln the usual form of computer system, information is transferred from the memory to peripheral equipment, such as the printer, in a block. The block is generally a set number of computer words which are equivalent to the number of words required to make up a single line of print. Once priority has been granted to the printer, the block of computer Words is transferred to the printer without interruption. Thus, if during this, transfer equipment of higher priority requests memory access the granting of such access is delayed until the transfer of the printer is com leted.

In an effort to make the transfer device more flexible, additional circuitry may he added to permit interruption during the transfer of a block of information from the memory to a particular peripheral unit. This circuitry may be quite complex in order to meet the needs of the peripheral equipment affected. Thus, in the printer device discussed above, means would have to be provided to keep track of the actual number of computer words transferred to the buffers of the printer, and those which remain to be transferred. Further, means would have to be provided to account for locations in a buffer register into which information has been placed and those which remain empty. Means would also have to be provided to prevent any printing of the data received until full line was assembled.

The present invention provides a high speed printing synchronizer which is able to overcome the difliculties and problems found in the prior art devices. It permits accounting for information as it is transferred to the high speed print buffers of a print synchronizer as Well as the detection of those conditions under which all information has been printed from the buffers to the paper, with the addition of only a small amount of equipment not normally found in high speed computer and data processing systems. The present invention obviates the necessity for large numbers of complex counters with their attendant circuitry which would be required by conventional approaches to the problems involved. The de vice of the present invention is able to determine how much information is stored within its print buffers; to determine whether additional requests for the transfer of information from the memory to the print buffers are required to fill them; to determine which characters stored within the print buffers have been printed out and to determine when all the characters which compose a particular line have been printed out so as to permit the printer to execute further print instructions.

It is, therefore, an object of this invention to provide a high speed print synchronizer capable of receiving information in a random fashion while accounting for all information received.

It is a further object of this invention to provide a high speed print synchronizer which employs a unique coding arrangement to permit the continual interrogation of the buffers contained within such high speed print synchronizer to determine the location of the last information entered within such buflers and further, to determine when these buffers have been completely filled.

It is a further object of this invention to provide a high speed print synchronizer capable of reading information from its internal buffers and printing out such information as the print characters are available, while keeping track of all information which has been so printed out.

It is a further object of this invention to provide a unique high speed printing synchronizer which employs a coding scheme to determine when information contained within the buffers of the high speed print synchronizer have been printed out in order to prevent further attempts to print out information already printed and detect when all information contained within such buffers have been printed out.

It is a further object of this invention to provide a high speed print synchronizer which by unique coding arrangement is able to determine (1) by the use of first coded bits placed in the characters of a word the location of the last word of information entered into the buffers of said print synchronizer, and from the same bits, to determine when said butfers register are completely full, and (2) to determine from a second coded bits placed in the characters of a word when information contained within the buffers have been printed out so as to provide that the same information will not be printed out a second time, and further employing said second coded bits to determine when all of the information contained within the buffers have been printed out.

It is yet anothesr object of this invention to provide a high speed print synchronizer capable of receiving information in its buffers in a random fashion, printing out such information as the print characters are available, capable of continuously monitoring the contents of its buffers to 

1. A SYNCHRONIZER FOR TRANSMITTING DATA IN THE FORM OF PULSES FROM A SOURCE TO A RECEIVER WHERE THE RATE OF DATA TRANSMISSION FROM THE SOURCE IS DIFFERENT FROM THE RATE OF DATA RECEPTION BY THE RECEIVER, SAID DATA COMPRISING SETS OF GROUPS OF PULSES, EACH GROUP HAVING A NUMBER OF PULSE POSITIONS WHEREIN A FIRST PORTION OF THE PULSE POSITIONS IS AVAILABLE FOR PULSES INDICATIVE OF A CHARACTER AND A SECOND PORTION IS AVAILABLE FOR CONTROL PULSES, AND EACH SET COMPRISES A NUMBER OF SAID GROUPS, SAID SYNCHRONIZER COMPRISING: A RECIRCULATING SHIFT REGISTER MEANS HAVING AN INPUT AND AN OUTPUT FOR RECEIVING A PLURALITY OF SETS OF GROUPS OF PULSES FROM SAID SOURCE; MEANS FOR AUTOMATICALLY INSERTING A PULSE INTO A SELECTED PULSE POSITION OF A SECOND PORTION OF SOME OF THE SAID GROUPS IN A SET AS SAID GROUPS OF A SET ARE RECEIVED BY SAID REGISTER MEANS, THE INSERTED PULSES IDENTIFYING THE LAST SET RECEIVED BY SAID REGISTER MEANS; AND CONTROL MEANS COUPLED TO SAID RECIRCULATING REGISTER MEANS AND GOVERNED BY SAID INSERTED PULSES OF SAID LAST SET, FOR CAUSING THE TRANSFER INTO SAID RECIRCULATING REGISTER MEANS OF THE NEXT SET IN A POSITION NEXT TO THE LAST SET PREVIOUSLY RECEIVED AND FOR ALTERING THE PAST COMBINATION IN A SECOND PORTION OF THE GROUPS COMPRISING THE SET PREVIOUSLY RERECEIVED. 